Friday, July 15, 2011

The Counter/Timer and Interrupt Inputs





The Models of 110CPU612, 110CPU411, and 110CPU512 of the Micro PLC have a set input points built into the hardware that can be constructed as high-speed hardware interrupts and/or counters. These inputs are placed on the left side of the terminal block of input across the top of the PLC.

These inputs can be understand on every scan by the PLC just like the input points of standard. Additionally, they can applied to hardware-initiated subroutine or to trigger high-speed counting operations in ladder logic. They are addressed to references 10081 - 10088 in the I/O map of the linked PLC when they are utilized as standard inputs. When they are used to high-speed counting or trigger interrupts operations, these inputs require to be constructed in ladder logic through an instruction called CTIF. CTIF constructs the interrupt to internal high-speed and hardware counter for use with these high speed inputs. CTIF-arranged inputs do not require to be addressed in the map of I/O unless their connected references are utilized in the ladder logic program.

Interrupt of Operation Hardware
A low-to-high transition on the input starts a service subroutine to interrupt when a hardware break off is constructed. Interrupt-initiated subroutines are very alike to the subroutines of JSR-initiated. They break off the normal logic scan and transfer it to an instruction of LAB in segment 2 that recognizes the starting of appropriate subroutine. The subroutine performs until the scan encounters an instruction of RET, at which point the logic scan goes back to its previous location in segment 1. The primary difference is that the subroutine of interrupt-initiated is triggered by an external occasion caused by a hardwired device to the input, while the JSR-started subroutine is activated by internal conditions in the logic program.

To start more than one interrupt on the same input, the signal of interrupt have to go low then changeover back to high again. The operating system of ladder logic does not permit a new interrupt on the similar input until the previous interrupt subroutine has been finished for about 2 ms. This delay avoids a PLC lock-up that could or else be caused by a high speed continuous stream ( > 2 ms) breaks off at the input. The dedicated break off is linked to the CPU in the PLC throughout a hardware filter, which introduces around 50 ms of interruption into the interrupt subroutine. The operating system also operates with the interrupts disabled for a convinced time in every scan—around 300 ms. Therefore, the interrupt subroutine initiation could be postponed by approximately 350 ms.



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