The fundamental Solidstate Logic Solver (SLS) circuit element is a core of ring-shaped magnetic material with some windings. This essential circuit more consists of a pulse shaping and transistor circuit that includes a diode and a choke coil. The core of ring-shaped magnetic is not a usual transformer, since it has a very high hysteresis, which builds it an element of binary with two stable positions and it provides a dual purpose. First it can perform logical functions such as AND, OR, NOT and secondly it does give an isolation of galvanic between Solidstate Logic Solver (SLS) circuits.
Current pulse-trains are utilized to magnetize the magnetic cores. The responsibility cycle is fewer than 3%, which maintains the dissipation of circuit low. As an extra advantage, as a effect of this principle of current the low circuit impedances create the circuit resistant to electro-magnetic interference high levels. The logical input information ‘1’, from a closed field contact for instance, is symbolized by a pulse-train of 1000 short pulses per sec in the circuit of SLS (Solidstate Logic Solver); it calls them pulses ‘A’. Every circuit of Solidstate Logic Solver (SLS) requires these ‘A’ as well as phase shifted pulses of ‘B’, which may originate from the other logic input or from the generator of system clock.
These current pulse-trains of ‘A’ and ‘B’ have a shape of asymmetrical, meaning that the flows of current in one direction only and consequently are only able to magnetize the core in only one direction. A second wire throughout the similar core, having pulses in the reverse current direction and which are shifted phase, ensure that the approximately rectangular hysteresis-loop of the cores of magnetic is fully used. The resulting pulse-train of output is alternating between pulses of positive and negative. Only the pulses positive are able to create the transistor conduct. Only in case that both pulses ‘A’ and ‘B’ are present, an induced pulse-train of current will come out of the lift up winding, during the magnetic flux changing. This pulse train creates the transistor turn ‘ON’ with every positive pulse, making this Solidstate Logic Solver (SLS) basic-circuit output with a same pulse-train.
It will be obvious, that the above circuit can be implemented as a logical gate of ‘AND’ when ‘A’ and ‘B’ stand for two logical signals of input. An extra wire throughout the core with pulses ‘A’- in the similar direction will make a logical gate of ‘OR’, assume that the pulses ‘B’ come from the clock system. The output will constantly go to a static de-energized state, whenever any failure of component or a wire fault happens.