Thursday, December 1, 2011

Yokogawa PLC Performance with Synopsys Processor

•Designer of Processor automates the custom processors design giving IP block designers an easy−to−use as part of Synopsys' System−Level Design portfolio, high performance option to making fixed processing application or hardware.
•Profiling feature of Processor Designer's allowed Yokogawa to discover and optimize their processor to reach processing performance of ladder program that is 5X faster than earlier versions.
•Yokogawa saved significant development and time of verification by automatically creating software development tools by using Processor Designer.

Synopsys, Inc. a world leader in IP for semiconductor and software design, verification and manufacturing, has announced that Yokogawa Electric Corporation applied Synopsys Processor Designer to reach ultrafast processing performance of ladder program for their newest FA−M3V PLC. Yokogawa also improved significant development and verification attempt with Processor Designer since the device automatically produces tools of software development such as assembler/linker, C−compiler, the instruction set simulator (ISS) and debugger required for early development of software earlier than processor availability.

The latest PLC FA−M3V has accomplished the fastest performance that ever seen with the latest core customized of Vitesse Engine for processing of ladder language program. They were capable to build up this ultra−high performance processor with significantly less time and effort than they initially designed with Processor Designer. Yokogawa realized their improvements in time savings and performance by leveraging capability of Processor Designer's profiling to discover and optimize the architecture of processor. These optimizations allowed Yokogawa to meet their goal performance of ladder program processing of 3.75 nanoSeconds/instruction − 5X faster than earlier versions. By optimizing the specification of LISA language input and therefore the resulting code of RTL, the team of design also decreased power, count of gate and total time of system development en route to a victorious tape−out.

Processor Designer spectacularly goes faster the design of both application, specific processors and configurable accelerators throughout development tools of automated software, ISS generation and RTL from a single, high−level specification. These specific processors application and accelerators configuration are more and more vital to support the multiple functionalities convergence on a single SoC (system on chip). It is applied to increase a large range architectures of processor, comprising architectures with specific features of DSP and RISC, as well as SIMD (single instruction multiple data) and VLIW (very long instruction word) processors.

Yokogawa are finding they can improve significant development attempt and accomplish better quality of results by automating the design process of application specific instruction set processor (ASIP). The Companies developing fixed processing hardware or ASIP in−house increase flexibility of broad architectural to compact with growing requirements without compromise the performance, area or power.


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