Thursday, March 15, 2012

Design for Host Controller of PLC





The module of central control is the PLC system core module. It includes a CPU acted by embedded microprocessor of 32-bit, various expanded memory, analog input and interface circuit output, some interfaces of I/O set by one FPGA, and a coprocessor executed control arithmetic by another particular FPGA the arithmetic control is considered as subprogram function called by the PLC ladder chart main program, which create the coprocessor operation time does not engage the user program execution time. The system accesses CAN bus by microprocessor SPI-port. The PLC central controller structure diagram is shown in figure below.

Design for memory modules
The module of PLC central controller require a great capacity nonvolatile Flash memory which could be utilized to save the bootstrap program, FPGA configuration, explaining and communication user's program. But it is also required that SDRAM (synchronous dynamic random access memory) utilized to save data, a great capacity nonvolatile Flash memory that could be written in and read out online, and EEPROM (electrically erasable programmable read only memory) preventing lost data when the processor loses power.

A flash memory of 16MB supplied with 3 Volts is utilized for MSF (mass storage facility), which has data 16 bits width and takes typical bus interface to interrelate with the processor. The MSF reading out require not any special codes but the hardware OM1-O and B/S ports should be set so that the processor could determine the data length orders in the flash memory. The bootstrap utilized to start up the system has to be mapped into BankO processor address because it saves in the flash memory. The processor would find the instruction automatically from address Ox00000000 to start up the system which having been energized and reset.Fig below is interface circuit diagram between flash memory and ARM. The 'ADDR24' 1 'of ARM processor connect correspondingly to the flash memory of A23 O, that is, the address compensates leftward one bit because ARM is facility of byte-addressable while gets 16 bits(2 bytes) perform as one storage unit in ROM flash. As a mapping relation result between the processor and flash ROM, the signal of chip-select nCE connects with microprocessor 'nGCSO'port.

In this method the PLC scanning program cycle and the system run speed could be improved. Every SDRAM (HY57V64 1 620) supplied with 3.3 Volts in the system has capacity of 8MB and width 16 bits data, which supports automatically stimulating by it and is mapped into BankO processor address.



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